INTERFACE STATES IN III-V COMPOUND SEMICONDUCTOR MOS DEVICES

The impediment to full scale GaAs integrated circuit development has been the lack of a good quality passivating material for the GaAs surface similar to the Si-SiO(,2) system. Of critical importance to device performance is the electrical properties of the interface between the passivation layer and the semiconductor. In this study, the electrical characteristics of the interface between an anodic native oxide of GaAs formed in tartaric acid, water and propylene glycol and GaAs itself are studied. In particular, the energy distribution of the interface state density of the native oxide-GaAs system is investigated. The MOS capacitors are fabricated from n(100), n(111)B, and p(100) material. The Ta(,2)O(,5)/native oxide passivation layer is also studied. Variable frequency capacitance and conductance measurements as a function of bias are used to determine interface state density. In particular, the quasistatic and conductance methods are employed. The devices exhibit hysteresis due to electron injection into the oxide and anomalous frequency dispersion of the accumulation capacitance. These effects are shown to be consistent with the interface state and oxide trap model. The surface potential as a function of applied bias is also determined and is found to restrict the Fermi level to the lower half of the bandgap. The range of allowed Fermi level movement is .43 eV. Minimum densities of 10('12) eV('-1) cm('-2) are found while no maximum is detected. The conductance determination of state density is consistent with the capacitance method. In addition, the spacial distribution of the states is found. Single level bulk impurity states are located at .75 eV and 1.1 eV below the conduction band. Oxide traps distributed uniformly in the oxide at least to a depth of 16 (ANGSTROM) also exist. Both the single level states and the oxide traps contribute to losses which are measured at the interfaces. Losses due to the oxide traps are also influence by the statistical fluctuation of the surface potential. Because the high state densities on each side of the minimum restrict Fermi level movement n-type accumulation and p-type inversion MOS devices are prohibited. The depletion condition is allowed. Charge storage times in excess of 40 seconds are seen for n-type MOS devices. This study indicates only depletion type MOS devices can be fabricated employing the anodic native oxide-GaAs material system.